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700 East Middlefield Road
United States of America
001 650 584-5000
Synopsys today announced that its DesignWare PHY and digital controller IP for the PCI-SIG PCI Express 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCI Express 3.0.
Synopsys today announced that Achronix Semiconductor has successfully used both Synopsys' IC Compiler physical design and IC Validator physical verification solutions to sign off its Speedster22i FPGA – the industry's first system-on-chip design using FinFET transistors.
Synopsys announced it will report results for the second quarter fiscal year 2013 on Wednesday, May 22, 2013, after the market close. A conference call to review the results will begin at 2:00 p.m. PT (5:00 p.m. ET) and will be hosted by Aart de Geus, chairman and co-chief executive officer, and Brian Beattie, chief financial officer.
Synopsys announce that HiSilicon Technologies has taped out a 50+ million instance ARM Cortex-A15 processor based SoC using Synopsys' IC Compiler, a key component of Synopsys' Galaxy Implementation Platform. The latest technology innovations in IC Compiler, including improved clock tree synthesis and faster top-level closure, were key to meeting performance and schedule on this gigascale SoC.
Synopsys today announced the availability of the 2013.03 release of its IC Compiler software, a key component of Synopsys' Galaxy Implementation Platform. Adding to the market-leading foundation of design closure technologies already available in IC Compiler, this latest release features innovations to speed design as well as enables the latest process nodes.
Synopsys today announced the immediate availability of the Embedded Vision Development System, an integrated solution for the acceleration of the design of processors for embedded vision based on Synopsys' Processor Designer tool set and Synopsys' HAPS FPGA-based prototyping system.
Synopsys are pleased to announce today that LG Electronics has adopted the IC Validator, Synopsys' physical verification applications tool, as part of their design implementation flow just for ARM processors. Key to LG Electronics' adoption was IC Validator's In-Design technology integration with Synopsys' IC Compiler™ place-and-route solution.
Synopsys today announced that Fujitsu Semiconductor is successfully shipping a 2G/3G/4G baseband processor using Synopsys' DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP. Fujitsu Semiconductor selected Synopsys' silicon-proven IP to mitigate project schedule risks and help ensure the long-term interoperability of their ASIC design customer's system-on-chip with Fujitsu Semiconductor's RFIC products.
Synopsys announce immediate availability of its PrimeTime ADV solution, a new configuration of its market-leading PrimeTime static timing analysis and signoff product. PrimeTime ADV includes advanced leakage recovery and will incorporate physical-aware signoff-driven engineering change order guidance technology, which work in conjunction with the latest innovations for Synopsys' IC Compiler solution to enable the fastest path to timing closure and the lowest leakage power for gigahertz IC design implementation.
Synopsys reveal advances in its Galaxy Implementation Platform with the introduction of Galaxy Custom Router technology. The new Galaxy Custom Router provides automatic routing for complex high-speed digital and mixed-signals nets that require carefully crafted, high-quality layouts, such as shielded buses or nets, differential pairs, twisted pairs and matched resistance and capacitance routing.
ARM and Synopsys announce availability of optimized 28-nanometer Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect. The companies collaborated to deliver these optimized implementations in TSMC 28HPM process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP technology for core-hardening acceleration specifically optimized for Cortex-A15 and Cortex-A7 processor implementations.
Synopsys today announced the adoption of Synopsys' Proteus LRC by MagnaChip Semiconductor Corporation. MagnaChip uses Proteus LRC in their production mask synthesis flow to identify hotspot locations in designs that are sensitive to variations in the manufacturing process.
ARM and Synopsys have today revealed collaboration to optimize performance of ARM Mali graphics processing units in 20-nanometer and smaller process geometries using the Synopsys Galaxy Implementation Platform. The companies successfully taped out the first ARM Mali-T658 design using a 20nm process technology, ARM Artisan physical IP and shader functionality.
Synopsys today reported results for its first quarter of fiscal year 2013. For the first quarter of fiscal year 2013, Synopsys reported revenue of $475.1 million, compared to $425.5 million for the first quarter of fiscal 2012, an increase of 11.7 percent.
Synopsys has revealed the extension of its software development tools offering for ARM processor-based systems with the VDK Family for ARMv8 Processors. Synopsys Virtualizer Development Kits are software development kits using virtual prototypes as the embedded target. The new VDK Family builds on the success of the VDK Family for ARMv7 Processors, which Synopsys announced last year.
Synopsys today announced the availability of the latest release of its FineSim circuit simulator. The 2012.12 release of FineSim introduces new algorithms for layout resistance and capacitance parasitic reduction and complex on-chip power network simulation, enabling up to 2X simulation speed-up and capacity for post-layout simulation of a broad range of memory designs compared to previous versions of FineSim.
Synopsys today announced that United Microelectronics Corporation has selected Synopsys' IC Validator physical verification product for lithography hot-spot checking at the 28-nm process node. UMC standardized on IC Validator pattern matching, a patented technology enabling ultra-fast detection of manufacturing-limiting layouts, which can dramatically accelerate final design signoff.
Synopsys today announced it will report results for the first quarter fiscal year 2013 on Wednesday, Feb. 20, 2013, after the market close. A conference call to review the results will begin at 2:00 p.m and will be hosted by Aart de Geus, chairman and co-chief executive officer, and Brian Beattie, chief financial officer.
Synopsys today announced Imagination Technologies has deployed Synopsys' C–to-RTL formal consistency checking technology, named HECTOR, to verify its PowerVR family of semiconductor IP cores for graphics, video and display processing applications. Following a multi-year collaboration with Synopsys, Imagination Technologies is utilizing HECTOR to enhance its verification environment with the ability to verify and debug corner cases.
Synopsys has today announced the availability of its multiprotocol DesignWare Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer Enterprise 10G PHY supports multiple interface standards, including PCI Express 3.0 and 10GBASE-KR, for a flexible interconnect solution.
Synopsys today announced the availability of version 8.0 of its LightTools illumination design software, which delivers multi-CPU support that dramatically improves the speed of lighting system simulations. With the addition of several new 3D objects, application-specific utilities and enhancements to parametric controls, this version also provides features that simplify the design of state-of-the-art lighting components.
Synopsys today announced that Oticon has standardized on Synopsys' Galaxy Implementation Platform and Lynx Design System for low power implementation. The advanced capabilities and extensive support for IEEE-1801 Unified Power Format in the Synopsys solution enabled Oticon to meet an aggressive 400 microwatt power budget while operating well below one volt for its next-generation multi-core DSP-based IC.
Synopsys announced immediate availability of its comprehensive solution for FinFET-based semiconductor designs. The solution includes a range of DesignWare Embedded Memory and Logic Library IP ; silicon-proven design tools from the Galaxy Implementation Platform; and foundry-endorsed extraction, simulation and modeling tools.
Synopsys today announced that it has contributed the specification and definition of Python PCell (PyCell) API technology to the IPL Alliance. The contribution will benefit the custom design community by allowing IPL member companies to be directly involved in the evolution of the Interoperable Process Design Kit (iPDK) standard.
Synopsys today announced advancements in its longstanding verification collaboration with Freescale Semiconductor. With a focus on addressing the increasing complexities of system-on-chip (SoC) verification, Freescale teams are leveraging Synopsys' innovations in next-generation verification IP (VIP), simulation performance, debug technology and methodology development.
Synopsy announce that Elliptic Technologies successfully deployed Synopsys' Discovery Verification IP for the ARM AMBA protocol for verification of its new-generation Multi-Packet Manager security protocol accelerator (CLP-630). Elliptic cited performance, efficient ease-of-use and smooth deployment as some of the key benefits of Discovery VIP.
Synopsys has completed the acquisition of SpringSoft through a follow-on merger to acquire all of the remaining outstanding shares of SpringSoft. Previously, on October 1, 2012, Synopsys completed a tender offer for approximately 91.64 percent of SpringSoft's outstanding Shares. As of November 30, 2012, Synopsys is the 100 percent owner of SpringSoft and SpringSoft stock is no longer trading.
Synopsys today announced the availability of Synopsys' HAPS-70 Series FPGA-based prototyping systems, extending its HAPS product line to address the increasing size and complexity of system-on-chip designs. The HAPS-70 systems provide tightly integrated prototyping software and hardware, including high-speed time-domain multiplexing (HSTDM) technology, which in combination with new HapsTrak 3 I/O connectors delivers up to 3x prototype performance improvement over traditional connector and pin multiplexing technology.
Synopsys today announced a new release of its DesignWare STAR Memory System, an automated pre- and post-silicon memory test, debug, diagnostic and repair solution that enables designers to improve quality of results, reduce design time, lower test costs and optimize manufacturing yield.
Synopsys today announced that ST has adopted Synopsys' volume diagnostics solution company-wide for faster yield ramp. IC product teams must rapidly isolate and correct systematic failure mechanisms to ramp up new IC designs from low initial yield to mature yield in volume production.
Synopsys today announced that its next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol now offers a Performance Checker capability. This capability enables system-on-chip (SoC) verification teams to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks.
Synopsys today announced that Synopsys' IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (DRC) and layout-vs.-schematic (LVS) runsets to UMC customers.
Synopsys today announced 20-nanometer (nm) process technology support for the TSMC 20nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20nm design rules and models.
Synopsys today announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS (Chip on Wafer on Substrate) Reference Flow. The design flow is the result of the latest collaboration between the companies on 3D-IC integration technologies.
IC Compiler is a cornerstone of the Synopsys Galaxy Implementation Platform, and its advanced optimization technologies, unique leakage power recovery capability and predictable flow with Synopsys Design Compiler Graphical synthesis solution were key contributors to Open-Silicon achieving the performance and power targets and predictable timing closure for the hardened processor core.
Synopsys have unveiled two new products today: the DesignWare MIPI UniPro Controller for host and device storage, camera and display applications, and the DesignWare UFS Host Controller for storage applications. The new IP works in tandem with the multi-gear DesignWare MIPI M-PHY IP to accelerate the implementation of the MIPI Alliance UniPro and UFS interface standards in application processors, mobile systems-on-chips and peripheral ICs.
Synopsys today announced that the Synopsys Silicon Valley Science and Technology Outreach Foundation has reached a major milestone of providing more than one million unique experiences to students and teachers developing science projects since the program's inception in 1999. Experiences include support for science project development, science fair sponsorship, competitions and teacher training offered through a range of Foundation programs.
Synopsys has revealed today that Hitachi has selected Synopsys' Discovery Verification IP for the ARM AMBA AXI3 protocol for verification of Hitachi Virtual Storage Platform. Enabled by Synopsys' next-generation VIPER architecture, Discovery VIP demonstrated a performance advantage over other VIP, as well as delivered protocol-aware debug capabilities and advanced built-in coverage features, which have accelerated Hitachi's Storage Systems verification closure process.
Synopsys announced today that it has obtained regulatory approval in Taiwan to acquire SpringSoft, Inc. In addition, greater than 51 percent of the outstanding shares of SpringSoft have been tendered. By meeting these two milestones, Synopsys expects to complete the tender offer and take a controlling interest in SpringSoft as of October 1, 2012.
Synopsys has today announced that it has enhanced it DesignWare DDR Memory Interface IP portfolio with the release of support for DDR4 SDRAMs. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip, which is a key requirement of many SoCs such as applications processors for smartphones and tablets.
Synopsys today announce the release of IC Validator 2012.06, Synopsys' physical verification platform for advanced process nodes. With immediate availability of qualified rule decks by leading foundries, IC Validator 2012.06 offers new technologies that enable physical signoff verification at advanced process nodes.
Synopsys today announce the availability of the latest release of its RSoft Optical Communication Design Suite, which includes OptSim and its multimode companion tool ModeSYS. OptSim version 5.3 delivers innovative modeling capabilities and new application examples that enable engineers to accelerate the design of high-performance optical communication systems.
Synopsys has today announced that John Chilton, senior vice president of marketing and corporate development, will speak at Deutsche Bank's dbAccess 2012 Technology Conference in Las Vegas, on Sept. 11, 2012.
Synopsys has today revealed the 100th design win of its DesignWare IP optimized for 28-nm processes for multiple leading foundries. The silicon-proven 28-nm portfolio consists of widely-used IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens of millions of units shipped.
Synopsys has today revealed results for its third quarter of fiscal year 2012. For the third quarter of fiscal year 2012, Synopsys reported revenue of $443.7 million, compared to $386.8 million for the third quarter of fiscal year 2011, an increase of 14.8 percent.
Synopsys today revealed that University of Rochester students Anthony Visconti and Brett Sternfield and University of Alabama in Huntsville student Josh Walters are the winners of the 2012 Robert S. Hilbert Memorial Optical Design Competition.
Synopsys has annoucned today that it will report results for the third quarter of fiscal year 2012 on Wednesday, Aug. 22, 2012, after the market close. A conference call to review the results will begin at 2:00 p.m. PT (5:00 p.m. ET) and will be hosted by Aart de Geus, chairman and co-chief executive officer, and Brian Beattie, chief financial officer.
Synopsys has today revealed that the Seventh Annual International Microelectronics Olympiad of Armenia will be held on October 4, 2012 in Yerevan, Armenia. For the first time, the event will be held in cooperation with the Institute of Electrical and Electronics Engineers Test Technology Technical Council. IEEE's participation highlights the contest's growing international reputation.
Synopsys has today launched VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip verification engineers and users of verification IP. The site provides a centralized online resource of relevant forums and blogs focused on verification of industry-standard protocols.
Synopsys announces today that it has signed a definitive agreement to acquire SpringSoft. The SpringSoft acquisition supports Synopsys' strategy to quickly and effectively deliver the advanced capabilities that will help semiconductor customers solve their toughest design challenges, including verification and custom implementation.