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Mentor Graphics Corp today announced it has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process. The prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a photonic layer and interconnects also holds the promise of solving speed bottlenecks in future computing and chip platforms.
Mentor Graphics and Tezzaron Semiconductor today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron's 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features.
Mentor Graphics today announced that CNH has transitioned to the latest VeSys software platform and also added a number of compatible tools from the Mentor Capital software suite, resulting in a very modern design environment.
Mentor Graphics today announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company's cost models.
Mentor Graphics today announced release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon.
Mentor Graphics and Agilent Technologies are pleased to announce today the use of the Mentor Graphics BridgePoint xtUML environment in the development of its Micro GC gas chromatography instruments.
Mentor Graphics today announced hardware and software solutions to accelerate the verification of Serial Attached SCSI second-generation products, having speeds up to 6Gbps. Using the Mentor verification solutions, designers can test their SAS Gen2 devices integrated on their System-on-Chip designs, and develop and test their software drivers and applications prior to silicon being available.
Mentor Graphics today announced the Nucleus SmartFit product, a cost-effective, binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs. The Nucleus SmartFit product also includes Sourcery CodeBench development tools and provides developers with broad connectivity and power consumption options for developing products based on 32-bit microcontrollers.
Mentor Graphics today announced availability of the first, comprehensive IP to System, UPF-based low-power verification flow. The IEEE-1801 UPF has emerged as the low- power standard that enables designers to specify a design's power intent separately from the design itself ensuring reuse, portability and greater flexibility in power management techniques.
Mentor Graphics announce financial results for the company's fiscal fourth quarter and year ended January 31, 2013. The company reported revenues of $331.2 million, non-GAAP earnings per share of $.58, and GAAP earnings per share of $.49. For the full fiscal year, revenues were $1,088.7 million, non-GAAP earnings per share were a record $1.42, and GAAP earnings per share were $1.17.
Mentor Graphics today announced availability of the Kronos Cell Characterization and Analysis platform. The Kronos platform quickly produces accurate performance models for standard cells, I/Os, and complex cells within an advanced, integrated environment.
Mentor Graphics today announced the 10.2 release of the Questa functional verification platform, a tightly integrated and extensible set of tools and solutions that is transforming the functional verification of complex System-on-Chip and FPGA designs.
Mentor Graphics today announced that its previously proprietary front-end UML editor has moved into the open source domain. Accessible for free download, this editor was formerly part of the company's powerful BridgePoint xtUML environment.
Mentor Graphics have today announced the newest release of its market-leading HyperLynx product for superior high-speed design and analysis. Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster.
Mentor Graphics today announced comprehensive design, manufacturing, and post tapeout enabling support for Samsung's 14nm IC manufacturing processes, providing customers with a complete design-to-silicon flow concurrent with early process availability. The fully interoperable Mentor flow helps customers achieve fast design cycles and first time silicon success.
Mentor Graphics has today revealed the introduction of new hardware and software solutions to accelerate the verification of PCI Express Generation 3 products. These new solutions, when connected to a Veloce emulator, enable designers to test the new generation PCI Express devices on their System-on-Chip designs, and to develop and test their software drivers and firmware prior to silicon being available.
Mentor Graphics announce new formal-based technologies in the Questa Verification Platform that provide mainstream users with the ability to more easily perform exhaustive formal verification analysis. The new Questa AutoCheck technology delivers fully automated formal checking analysis, while the Questa CoverCheck tool provides 100% code coverage closure. The Questa Verification Platform now also offers expanded clock-domain crossing capabilities.
Mentor Graphics today announced new capabilities to complement TSMC's 20nm manufacturing processes. Enhancements to support both digital and analog/mixed signal 20nm reference flows include new features in the PyxisT IC Station platform, the Eldo fast SPICE simulation products, the Olympus-SoCT place and route system, the CalibreR nmDRCT, Calibre RealTime, Calibre PERCT and Calibre xACT 3D solutions, and the TessentR silicon test product suite.
Mentor Graphics has revealed availability of an update to the popular Universal Verification Methodology Connect to bring the benefits of it to the Open Verification Methodology community. UVM Connect has been extended to allow it to be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.
Mentor Graphics Corp. today announced that its Capital tool suite has been accredited to IBM's "Ready for IBM Rational" program. This program validates integrations between the Rational Software Delivery Platform and adjacent applications such as the Capital tool suite, ensuring mutual customers benefit from seamless interoperability.
Mentor Graphics Corp. today announced the availability of the Veloce2 platform, the next-generation of emulation solutions for the verification of electronic system and Systems on Chip (SoC) designs. Built to accommodate up to two billion gate designs, the Veloce2 platform delivers twice the performance, twice the capacity and four times productivity gain in the same footprint and power consumption as the first-generation Veloce platform.
The next phase of semiconductor designs will see the adoption of 3D IC packages, vertical stacks of multiple bare die connected directly though the silicon. But TSVs complicate the test process and there is no time to waste in finding solutions. By Stephen Pateras.
Mentor Graphics Corporation today announced that Samsung Electronics and Mentor have successfully delivered a complete design-for-manufacturing (DFM) sign-off reference solution for Samsung's foundry customers based on the Calibre platform. The DFM sign-off solution is available for world class consumer and telecommunications designs targeting advanced process nodes. Samsung has already released the Calibre kits to their customers for 32 nm and 28 nm, and has completed evaluation for 20 nm.
Mentor Graphics Corporation today announced that it has acquired the Flowmaster Group, a global leader in 1D Computational Fluid Dynamics (CFD) simulation software for system design. 1D CFD solutions allow for very rapid engineering design of complex fluid flow network systems like water-cooled electronic racks, automotive vehicle thermal management, and aerospace fuel systems. This acquisition consolidates the position of Mentor Graphics as the first EDA company to move into the adjacent Computer-Aided Engineering (CAE) mechanical analysis space.
Mentor Graphics Corporation has announced that its industry-leading Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. This enables both hardware and software engineers to fully verify their multi-core ARM-based designs seamlessly across the Questa verification and Veloce emulation platforms.
Mentor Graphics has announced hardware and software solutions to accelerate the verification of Universal Serial Bus SuperSpeed (3.0) products. These new solutions, connected to a Veloce® emulator, enable designers to test their USB SuperSpeed peripheral devices integrated on their System-on-Chip (SoC) designs, and to develop and test their software drivers and firmware prior to silicon being available.
Mentor Graphics Corporation and NuFlare Technology, Inc. announced the extension of their successful collaboration on integrated hardware and software solutions for advanced IC mask generation. The companies' new joint marketing and support agreement will help ensure seamless interfaces, high mask fidelity, fast mask writing times, and very high levels of technical support.
Mentor Graphics Corporation announced new capabilities in the Tessent TestKompress and the Tessent FastScan tools that enable higher defect coverage and lower defect per million levels for quality-critical applications like military, medical, automotive, and many others. User defined fault models and a new cell-aware ATPG flow together allow customers to target subtle shorts and open defects internal to standard cells that are not adequately detected with the standard stuck-at or transition fault models.
Mentor Graphics Corporation announced a collaboration with TSMC to support SmartFill functionality in the Calibre® YieldEnhancer product for TSMC's manufacturing processes starting at 65nm. The analysis and automatic filling capabilities of the SmartFill solution allow designers to achieve IC fill constraints with minimal impact on circuit performance in a single pass without manual customization or modification.
Mentor Graphics Corporation has announced it has expanded the Vista™ ESL Platform to address the needs for Virtual Prototyping for early software development. In addition, the Vista ESL platform's integration with Catapult C, sharing common TLM modeling style for Virtual prototyping and HLS-based hardware implementation, has been strengthened with the Mentor® partnership with Calypto. The Vista ESL platform is the center point of the Mentor comprehensive ESL strategy, a strategy that has extended the boundaries of ESL technologies by addressing a broad range of electronic system design, virtual prototyping, hardware realization, software realization, and TLM-to-RTL verification and model reuse challenges.
Mentor Graphics Corporation has announced the call-for-entries of its 23rd annual Technology Leadership Awards competition, continuing its tradition of recognizing excellence in printed circuit board (PCB) design. Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. It recognizes engineers and CAD designers who use Mentor Graphics® innovative technology to address today's complex PCB systems design challenges and produce industry-leading products.
Mentor Graphics has announced that the PyxisTM Custom IC Design Platform is available immediately, delivering new functionality and increased productivity through advances in concurrent design and automated custom IC routing technology. The Pyxis Custom IC Design Platform is a step function improvement to current custom IC design and verification tools by addressing their most serious shortcomings
Mentor Graphics announced that the Mentor Verification Academy website, which provides access to information and online training on advanced functional verification technologies, has been expanded to serve the growing information requirements of companies adopting the Universal Verification Methodology (UVM) and the Open Verification Methodology (OVM). The use of these methodologies has skyrocketed in recent years as they continue to deliver on the promise of improved design and verification productivity, verification data portability, and tool and verification IP (VIP) interoperability.
Mentor Graphics announced a unified embedded software debugging platform, from pre-silicon to final product, based on the integration of the Mentor Embedded Sourcery CodeBench embedded software development tools with Mentor's leading electronic system level (ESL), verification, and hardware emulation products. These include the Mentor Graphics® Vista™ Virtual Prototyping product, Veloce® hardware emulator, prototype target boards, and end products or any combination thereof. The new common platform, being shown at the Mentor booth #1542 at DAC, enables embedded software developers to access technology data from hardware design tools without leaving their native embedded software environment.
Mentor Graphics announced today a significant expansion of the company's Capital product suite. Already offering a powerful electrical system and wire harness design flow for the automotive, aerospace and defence industries, the Capital suite now includes three new products that extend that flow both upstream and downstream. With the introduction of new tools addressing configuration complexity, harness manufacturing and vehicle documentation and maintenance, Capital now delivers coverage from product definition to service technician. Employing breakthrough technologies, the new tools have high commercial value for platform OEMs, wire harness manufacturers and service organizations.
Mentor Graphics announced that the Catapult C high-level synthesis tool now supports the synthesis of transaction level models (TLMs). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista™ platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms. Expanding its full-chip synthesis technology, the Catapult C tool now delivers a methodology and a set of models to support TLM synthesis. With the new TLM synthesis flow, abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. Conversely, existing synthesizable descriptions can be converted to TLMs. The flow supports standard off-the-shelf bus interfaces, including the ARM AMBA bus family, as well as custom protocols. This new capability provides an essential link between virtual prototyping and HLS-based hardware implementation. Traditionally, these two activities have been separated by incompatible abstraction requirements: virtual prototyping relying on fast and abstract TLM interfaces, and HLS requiring pin-accurate synthesizable models. With its new TLM synthesis capabilities, the Catapult C tool closes this gap and, combining with Vista, opens new opportunities in ESL design, verification and virtual prototyping. "Eighty-seven percent of the respondents in a recent survey said it was either mandatory or highly desirable to have high-level synthesis tools integrated with ESL flows," said Simon Bloch, vice president and general manager, Design and Synthesis division at Mentor Graphics. "TLM synthesis leverages Mentor's strong technology 'know how' in both high-level synthesis with Catapult C and virtual prototyping with the Vista platform as a pivotal starting point for new levels of ESL flow integration." Synthesis-ready virtual platforms leverage standard TLM interfaces to combine simulation and synthesizable models. This allows joint design and verification at both the platform and the IP levels using a single and consistent ESL model. Hardware design teams can create abstract TLM models to be automatically synthesized to production quality RTL code using the Catapult C tool. At the same time, those models can be shared with the platform team for system integration, early software testing and fast ESL verification using Vista. Uniting TLM synthesis and simulation effectively creates convergence of ESL models and flows.
Mentor Graphics announced that it has received the Circuits Assembly Magazine New Product Introduction (NPI) Award for the Valor® vManageTM Materials Manager product in the Software-Management category.
Mentor Graphics announced that, according to the Electronic Design Automation (EDA) Consortium Market Statistics Service Report for 2010, the company has achieved a 50% worldwide market share in PCB design solutions. For over 12 years, Mentor Graphics® has been consistently executing on a vision and investment strategy to bring the most advanced design capabilities to the industry. Today, Mentor is supplying industry-unique capabilities that extend beyond the design of the PCB and integrate the multiple engineering disciplines necessary for complete product development and delivery.
Mentor Graphics announced it has expanded the use of low power verification capabilities in TSMC's Reference Flow 11 to address today's complex integrated circuit (IC) low power functional verification requirements. The Mentor® low power verification tool suite includes the Questa® functional verification platform, the 0-In® CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro™ equivalence checking tool.
Mentor Graphics announced the results of an extensive evaluation by the Tokyo-based Semiconductor Technology Academic Research Center (STARC) that showed the Calibre® xACT 3D extraction product delivers both reference level accuracy and high performance, enabling very high quality extraction for large IPs.
Mentor Graphics Corp. (NASDAQ: MENT), a leader in high-performance system verification solutions, today announced its next-generation platform to accelerate the verification of 100-Gigabit Ethernet products.
Mentor Graphics Corporation (NASDAQ: MENT) today announced that JEDEC, the organization dedicated to open standards in the microelectronics industry, has approved a thermal transient testing-based measurement methodology inspired by an original idea published jointly by the Mentor Graphics® MicReD® group and the Automotive Power Application group of Infineon in 2005.
Mentor Graphics Corporation today announced evaluation results at Fujitsu Semiconductor Ltd. that shows the Tessent YieldInsight diagnosis-driven yield analysis tool can help cut the time required to determine the cause of IC yield loss. By correlating production test results and physical design information, the product reduces the time to pinpoint yield loss mechanisms without requiring intimate knowledge of the manufacturing process.
Mentor Graphics Corp. today announced a Multimedia platform to accelerate the verification of 3D TV-based products.
Mentor Graphics Corporation today announced the new Calibre RealTime platform for signoff-quality physical verification during design creation. The first release provides instantaneous design rule checking (DRC) in the SpringSoft Laker™ custom IC design and layout solution, using the same Calibre decks as the signoff flow.
Mentor Graphics Corp. today announced that it assisted CamSemi in replacing their integrated circuit design and verification flow with Mentor tools to improve simulation performance and time to market.
Mentor Graphics Corporation today announced that its advanced synthesis products support Xilinx 28nm 7 series field programmable gate arrays (FPGAs). Xilinx 7 series FPGAs are built on a low-power and unified FPGA architecture that scales across low-cost and ultra high-end families. Support for the new 28nm Virtex-7 and Kintex-7 FPGA families is available now and support for Artix-7 will follow. Mentor Graphics is the first EDA FPGA synthesis provider to offer physical synthesis support for Virtex-7 and Kintex-7 FPGA designs.
Mentor Graphics Corporation today announced that Fujitsu Semiconductor Limited is now using the Calibre® PERC product for electrical rules checks that improve the correctness and reliability of its IC designs before committing to manufacturing. The product, which automates electrical checks based on user-defined rules, is designed to address customers' need to improve reliability by identifying areas of vulnerability to catastrophic electrical failures in ICs during factory test, transport, and field operation. Among the specific checks being performed at Fujitsu Semiconductor are electrostatic discharge (ESD) protection circuit checking, cross-domain and multi-cross-domain protection checking, level shifter checking, and optimal ESD I/O placement checking.
Mentor Graphics announced that the Semiconductor Technology Academic Research Center, STARC, has successfully employed the Tessent™ TestKompress® product to expand its low power IC test methodology for ICs used in battery-powered mobile devices and other power-sensitive products. Using Mentor Graphics technology, STARC is able to detect bridge and small delay failures and to prevent IR drop and power noise in nanometer devices, while minimizing test time and IC power consumption during test.
Mentor Graphics announced it has successfully supported Infineon to improve Infineon's verification productivity and effectiveness by assessing the status quo and by jointly establishing improved SystemVerilog (SV) methodologies. Mentor supported Infineon in this deployment based on Mentor's functional verification solutions. The cornerstone of Infineon's new verification environment is the Questa® functional verification platform. The technologies linked with the Questa platform, when applied with the established methodologies, improve Infineon's verification process.