In a move to ease and speed the development of complex ICs, Cadence Design Systems introduce the Tempus Timing Signoff Solution, a new static timing analysis and closure tool designed to enable System-on-Chip developers to speed timing closure and move chip designs to fabrication quickly. The Tempus Timing Signoff Solution represents a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for faster tapeout while producing designs with less pessimism, area and power consumption.
Cadence Design Systems today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs.
Cadence Design Systems today announced its intent to acquire the IP business of Evatronix SA SKA, adding to its rapidly expanding IP offering. Based in Poland, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, Display, MIPI, and storage controllers, which are highly complementary to Cadence's IP offering.
Cadence Design Systems today introduced a new version of Incisive Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by thirty percent. The 13.1 release of Cadence Incisive Enterprise Simulator addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification for today's most complex SoCs.
Cadence Design Systems announced today that GLOBALFOUNDRIES has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20 and 14 nanometers. GLOBALFOUNDRIES is using the Cadence Pattern Classification and Pattern Matching Solutions because they enable up to four times faster design for manufacturing, which is key to improving customers' silicon yield and predictability.
Cadence Design Systems today announced results for the first quarter of fiscal year 2013. Cadence reported first quarter 2013 revenue of $354 million, compared to revenue of $316 million reported for the same period in 2012.
Cadence Design Systems announce an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs – from design analysis through signoff – and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.
Fulfilling the promise of performance and power scaling at 16 nanometers, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC's 16-nanometer FinFET manufacturing process.
Cadence Design Systems today announced that it has entered into a definitive agreement to acquire Tensilica for approximately $380 million in cash. Tensilica had approximately $30 million of cash as of December 31, 2012.
Cadence Design Systems today introduced the first commercially available design IP (IP) and verification IP (VIP) supporting the new Mobile PCI Express (M-PCIe) specification, which enables today's leading innovators to develop products with both PC-class performance and extended battery life.
Cadence Design Systems kicks off its worldwide series of user conferences, starting with CDNLive Silicon Valley, March 12 and 13 in Santa Clara. CDNLive conferences provide an excellent opportunity for Cadence customers to collaborate and dig deeper into the latest technologies and methodologies with Cadence experts.
Cadence Design Systems today announced its participation at DVCon 2013, the seminal conference for functional design and verification that takes place at the DoubleTree Hotel in San Jose, California on the 25-28 February 2013,
Cadence Design Systems today revealed the election of Young K. Sohn, president and chief strategy officer of Samsung Electronics to its board of directors. Mr. Sohn brings substantial industry, financial, operational and governance expertise to Cadence through his experience in executive leadership at leading semiconductor firms and advisory roles in investment firms. The company also announced the retirement of Donald L. Lucas from the board.
Cadence Design Systems today announced an agreement to acquire Cosmic Circuits Private Limited. Cosmic Circuits offers silicon-proven IP solutions in connectivity and advanced mixed-signal technologies in the 40nm and 28nm process nodes, with 20nm and FinFET development well underway.
Cadence Design Systems announced today that two of its major foundry partners—Samsung Foundry and GLOBALFOUNDRIES—are supporting new Cadence custom/analog technology targeting designs at the advanced nodes of 20 and 14 nanometers. The two foundries are providing SKILL-based process design kits for the newly introduced Cadence Virtuoso Advanced Node.
Cadence Design Systems announced today that GLOBALFOUNDRIES has certified essential Cadence technologies for custom/analog, digital and mixed-signal design, implementation, and verification for its 20-nanometer LPM technology. The certification covers the Virtuoso and Encounter platforms, including the industry-standard SKILL process design kit (PDK).
Cadence will introduce its joint development of advanced design technologies in partnership with the Common Platform Alliance (Samsung Electronics, IBM, and GLOBALFOUNDRIES) at the Common Platform Technology Forum on Feb. 5.
Cadence Design Systems has today announced production-proven verification IP for the new USB SuperSpeed Inter-Chip specification, enabling customers to thoroughly verify designs deploying the latest extension of the USB 3.0 protocol. The SSIC specification combines the MIPI Alliance physical interface with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device.
Cadence Design Systems today announced the availability of Virtuoso Advanced Node, a new set of breakthrough custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below.
Cadence Design Systems announced that Avago Technologies used Cadence Encounter Digital Implementation (EDI) System to accelerate the design schedule and boost engineering productivity on a large-scale 28-nanometer networking chip. Avago achieved performance of 1GHz, a 57 percent improvement compared to the previous software.
Cadence Design Systems introduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release. Incisive 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today's complex intellectual property (IP) and SoCs.
Cadence Design Systems have today announced its participation at embedded world 2013 to demonstrate the company's latest innovations of its Cadence System Development Suite. Visitors to Cadence's booth will have the opportunity to learn about the latest enhancements to the Cadence System Development Suite presented at this year's annual Cadence user conference CDNLive EMEA in Munich, Germany.
Cadence Design Systems announced today that Renesas Micro Systems has adopted the Cadence Encounter RTL Compiler for synthesis, highlighting a utilization improvement of 15 percent, area reduction of 8.4 percent, quick turnaround time, and cost reduction for complex ASIC designs.
Cadence have announced that Open-Silicon has leveraged the latest innovations from the Cadence Encounter RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nanometer hardening of an ARM dual-core Cortex -A9 processor.
Cadence Design Systems announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.
Cadence Design Systems today announced multiple successful verification projects using Cadence Verification IP for ARM AMBA protocols, one of the industry's most widely used verification solutions for the AMBA protocol family.
Cadence reported third quarter 2012 revenue of $339 million, compared to revenue of $292 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $59 million, or $0.21 per share on a diluted basis, including $15 million in acquisition-related income tax benefit, in the third quarter of 2012, compared to net income of $28 million, or $0.10 per share on a diluted basis in the same period in 2011.
Cadence have unveiled enhancements to its Allegro 16.6 Package Designer and System-in-Package Layout solution that support low-profile IC package requirements for next-generation smartphones, tablets, and ultra-thin notebook PCs. New features in Allegro 16.6 Package Designer and Cadence SiP Layout include open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package capability delivering the industry's most comprehensive design and analysis solution for IC package design.
Cadence Design Systems announced today that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms. The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.
Cadence Design Systems announced today that TSMC has validated Cadence 3D-IC technology for its CoWoS (chip-on-wafer-on-substrate) Reference Flow with the development of a CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP.
Cadence Design Systems announced today that its full suite of 3D-IC technologies were deployed by Taiwan's Industrial Technology Research Institute (ITRI) to develop a 3D-IC chip. Working together, engineers from Cadence and ITRI used the integrated Cadence 3D-IC flow to implement, analyze, and verify the test chip—a wide I/O memory stack with through-silicon vias (TSVs).
Cadence have launched the Incisive Debug Analyzer, a new and innovative verification debug product for RTL, testbench and SoC verification that offers significant reductions in debug time and effort. Cadence customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.
Cadence today announced the newest release of its Allegro printed circuit board technology, addressing customer need for a streamlined solution for efficient product creation. Allegro 16.6 accelerates timing closure for high-speed interfaces by 30-50 percent, through timing-aware physical implementation and verification delivered in the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
Cadence Design Systems today launched the Cadence OrCAD 16.6 PCB design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
Cadence has announced that it will showcase the company's expertise in memory design IP at MemCon 2012. Martin Lund, senior vice president of research and development, SoC Realization Group at Cadence, kicks off MemCon 2012 with his keynote speech, "How Cloud and Mobility are Disrupting the Memory Ecosystem" on Tuesday, September 18, from 9:30-10:00 AM.
Cadence Design Systems today announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property family have been proven in silicon on TSMC's 28HPM and 28HP process technologies.
Cadence and the National Research University of Electronic Technology (MIET) today announced the 10th anniversary of a graduate program in analogue and mixed-signal design for Russian engineering graduate students seeking a master's degree in electrical engineering.
Cadence have today reported financial results for the second quarter of the 2012 fiscal year. Cadence reported second quarter 2012 revenue of $326 million, compared to revenue of $283 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $36 million, or $0.13 per share on a diluted basis in the second quarter of 2012, compared to net income of $27 million, or $0.10 per share on a diluted basis in the same period in 2011.
Cadence have today revealed powerful new capabilities added to its PCI Express Verification IP which allow more in-depth verification of the most current PCI Express specification at both the block and system-on-chip levels.
Cadence Design Systems, Inc. has announced it has acquired Sigrity, Inc. Sigrity provides a rich set of gigabit signal and power network analysis technologies, including a unique power-aware signal integrity analysis capability for system, printed circuit board, and IC package designs.
Cadence Design Systems, Inc announced today that Ambarella realized significant improvements in power, performance and area on a recent 32-nanometer gigahertz SoC design by upgrading to the latest Cadence Encounter RTL-to-GDSII flow.
Cadence Design Systems, Inc. today announced that TSMC has qualified the Cadence Physical Verification System for 28-nanometer design signoff, and completed Phase I certification for TSMC's 20-nanometer process. Designers can request a PVS 20-nanometer technology file directly from TSMC for early design exploration, and access TSMC-Online to download 28-nanometer technology files for signoff.
Cadence Design Systems, Inc. today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals and SPICE models.
Cadence Design Systems, Inc. today announced its collaboration with TSMC on 3D-IC design infrastructure development. 3D-ICs require co-design, analysis and verification of heterogeneous chips and silicon carriers. Coming from multiple disciplines and product areas, TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC's first heterogeneous CoWoS vehicle.
Cadence Design Systems, Inc. today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling design at 20 nanometers and future process nodes.
Cadence Design Systems, Inc. today announced that the company's comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1. The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY's low-power interface and training features.
Cadence Design Systems, Inc. today announced that Nufront's NS115 chipset integrated the Cadence configurable DDR3/3L/LPDDR2 Memory Controller and Hard PHY IP core in its dual-core ARM Cortex-A9 based mobile applications processor. The TSMC 40nm LP 32-bit DDR3/3L/LPDDR2 interface features a data rate of up to 800Mbps while providing the automated traffic-based power management and efficiency critical to the ultrabook, tablet and smartphone markets.
Cadence Design Systems, Inc. today launched the industry's first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem.
Cadence Design Systems, Inc. continued its efforts to help customers reduce time to market for new systems and SoCs with the announcement of new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company's System Development Suite, and extensions to the Verification IP Catalog for acceleration and emulation to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.
Cadence Design Systems, Inc. today announced that Fujitsu Semiconductor Limited has adopted the newly updated Cadence Chip Planning System at its nine design centers spread around the globe. Fujitsu Semiconductor chose the Cadence system because of the time, accuracy and cost benefits it offers in the development of its MCU chips requiring large-scale integration (LSI).