Company Details
Aldec, Inc.
2260 Corporate Circle
Henderson
NV 89074
United States of America
Phone
+1 702 990 4400
Fax
Web Address
www.aldec.com
Aldec Delivers Prototyping Solution for Actel RTAX-S Space FPGA Designs
Aldec, Inc. has announced the availability of the RTAX-S Prototyping Board for radiation-tolerant RTAX-S FPGAs from Actel Corporation (NASDAQ:ACTL). Easing the prototyping process of space-flight systems, the new RTAX-S Prototyping Board provides the flexibility Actel's flash-based ProASIC3
FPGAs offer, allowing designers to utilize a design across multiple aerospace projects, shorten design cycles and lower project costs. Together with automatic primitive's conversion and reusability of the board, Aldec's early prototyping solution addresses challenges aerospace engineers may face during the verification process of a complex antifuse-based design.
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Aldec supports The MathWorks Simulink Fixed Point
Aldec has announced the release of co-simulation support for fixed-point in Simulink. Active-HDL coupled with The MathWorks Simulink provides support for fixed-point types and HDL co-simulation of
black-boxes, which allows seamless integration with Simulink-based DSP tools.
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Aldec Supports Altera's Stratix III Devices
Aldec, Inc has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family. SVE supports all aspects of system-level design development and verification. It includes an industry-leading common kernel HDL simulator, a set of on-line debuggers, code coverage, cross-probing tools and an industry-first integrated simulator server farm manager (SFM) for automatic verification of ultra-large system-level designs.
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Aldec Extends Code Coverage Analysis Offering
Aldec, Inc. has announced the addition of Expression Coverage for Verilog in the release of Riviera 2006.06. This addition significantly improves efficiency of the verification process and enables delivery of higher quality, more reliable designs.
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Altera's Quartus II 6.0 offers integrated HDL support for Aldec's Simulator
Aldec has announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment. Mutual customers can now select Aldec's HDL Simulator, Active-HDLT, directly from Altera's Quartus II software version 6.0.
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New SFM dramatically increases network based design verification
Aldec, known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced the release of Server Farm Manager (SFM). The new product dramatically increases network based design verification by automating the set-up, execution and analysis of simulation results from hundreds of computers running thousands of test cases and providing automated pass/fail results and reporting.
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