The module is complete with IM3910 MCU, SDRAM, flash memory, 10/100 Ethernet PHY (plus RMII interface for a 2nd Ethernet port), 3 UARTs, SPI/I2C, RTC, 8 timers, 8-ch ADC (16 bit), 2 DAC (16 bit), and a high-speed, 83 MB/s, data channel. The module is made for surface mounting (LCC84 standard footprint) and will be delivered on tape for automatic assembly.
This is the smallest (29*29 mm) and most cost efficient hardware module in Imsys’ SNAP family. Featuring the newest Imsys processor generation and providing full access to the processor’s features, it’s ideal for those needing a ready-made hardware/software platform for minimizing time-to-revenue for a networked product.
The SNAP Stamp is based on the Imsys IM3000 family of processors, which can process important routines – among them the Java bytecodes – internally, with dramatically increased efficiency. This allows user Java applications to run without the slowness of Java byte code interpretation or the need for a resource-hungry just-in-time compiler. Firmware and application software can be loaded, managed, and upgraded remotely through the network connection. The system software bundled with the module includes the Rubus™ real-time operating system, which is well proven in safety critical applications, the fail safe flash file system, with wear leveling and power fail recovery, the TCP/IP stack, J2ME/CLDC environment, Web / FTP / Telnet servers, device drivers for various I/O interfaces and an easy to use command line interface. The Java environment greatly accelerates development, increases software reliability, and eases deployment. “The Stamp is a big step in miimizing time–to-revenue”, says Stefan Blixt, Imsys’ CTO.
Java class files generated by any Java IDE (Eclipse, Netbeans) are directly executable on the SNAP Stamp. Development kit hardware and reference designs are available. The Imsys Developer (a complete Windows-based IDE) can be utilized for hardware debugging and software development in Java, C, and assembler, with breakpoints and single step debugging at all levels, dynamic variable inspection, event log, etc.
The microcode inside the core controls the processor logic and hardware resources and provides the abstraction layer used by the software. The architecture enables acceleration of CPU intensive tasks by orders of magnitude. Functions like jar file unpacking, garbage collection, bytecode interpretation, encryption, Ethernet MAC, audio playing, and video display are optimized in this way. The processor can therefore handle combinations of tasks that would otherwise require much more silicon and/or power consumption.