The dual core hard macro implementations are the result of ARM’s significant investment in advanced physical IP development in unison with processor and fabric IP technology, and leading-edge implementation flows from the EDA industry. Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.
The Cortex-A9 speed-optimized hard macro implementation will provide system designers with an industry standard ARM® processor incorporating aggressive low-power techniques to further extend ARM’s performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high-density and thermally constrained environments. This hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications.
In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
The hard macro implementations include ARM AMBA®-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSight™ Program Trace Macrocell (PTM) which provides full visibility into the processor’s instruction flow, enabling the software community to develop code for optimal performance.
“The Cortex-A9 MPCore processor has already been widely accepted as the processor of choice for high-performance embedded applications across a broad spectrum of demanding consumer and enterprise devices,” said Eric Schorn, VP marketing, Processor Division, ARM. “ARM’s parallel development of advanced, optimized physical IP components demonstrates a new level of collaborative differentiation while enabling our Partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures.”
“ARM’s long-standing investment in low-power leadership and ability to develop such high-performance devices enables licensees to lower the cost and risk of entering the high-margin markets currently addressed with competing proprietary solutions,” said Will Strauss, principal analyst at Forward Concepts. “With single-thread performance capable of supporting very intensive workloads, the unprecedented level of power efficiency will enable licensees to introduce compelling new products.”
“ARM and TSMC have enjoyed a long standing relationship of collaboration to ensure the development and delivery of best-in-class products optimized for our manufacturing process,” said ST Juang, Sr. Director, Design Infrastructure Marketing Division, TSMC. “This provides OEMs developing feature-rich consumer and enterprise devices access to TSMC’s manufacturing excellence and the power of ARM processor IP”
Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON™ technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
To enable the development of high-efficiency, low risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.
In addition, the ARM Active Assist consulting service, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realize maximum system performance with lowest risk and fastest time-to-market.