Power management design approaches
News Release from:
Lattice Semiconductor Corporation
09 August 2012
Power management designs typically begin in the same way. After system requirements are determined, a laundry list of discrete power management parts are analysed for a best fit for the design. Data sheets are reviewed and ASSPs from different vendors are checked to see if they are compatible.
A microprocessor can be utilised to give the system some timing flexibility. The final design is reviewed and additions, deletions or changes are made that usually result in wire additions and a few board spins.
There are several limitations to this traditional approach to power management design that affect time, cost and system reliability. Building an accurate power management design with discrete parts is expensive. For example, monitoring a system that requires +/-5% voltage tolerance using a low cost +/-2% supervisor will require an expensive +/-1% voltage regulator.
Relaxing these specifications on either the supervisor or regulator will result in the monitor creating additional spurious fault indications or will allow the system to operate below the lower limits of the Vnom -5%.
Creating a reliable, discrete power management design requires sets of fast comparators, precision references and precision resistors for each voltage, which are cost prohibitive. Discrete power management designs can also suffer from slow system response. Some designs take hundreds of milliseconds to respond to power fluctuations before disabling the input power and issuing system resets. Boards can be damaged from the overcurrent and in this amount of time microprocessors can overwrite an enormous amount of Flash with erroneous code.
Microprocessor-based power management designs are also slow to react because power monitoring is time-, not event-driven. Supervision only occurs when the microprocessor executes the part of the code that monitors the voltages or currents, taking tens of milliseconds to respond to a critical power event. Accurately monitoring voltages with a microprocessor usually requires the addition of an external precision voltage reference to compensate for the poor internal voltage reference, which is usually in the 2-4% tolerance range.
There are certain ASSPs that overcome timing and cost constraints by integrating all power management functions into a single IC. These are custom designed for high volume applications and can sometimes be used in other applications. The drawback to using an ASSP in another application is that usually not all of the system requirements are met, while other functions add cost but are not needed. PLC designs typically do not meet the high volume requirements to have an ASSP specifically designed for their many different card applications.
If this abstract has piqued your interest, read the full article online in the August issue of Electronic Specifier Design, by clicking here.