six-core DSP, TMS320C6472, digital signal processor, Texas Instruments
TI's new six-core, high-performance processors claim industry's best power efficiency
News Release from:
03 November 2009
Texas Instruments today announced the availability of the industry's most power efficient, six-core DSP (digital signal processor), the TMS320C6472, targeted at process-intensive applications requiring low power consumption. To help evaluate the performance of the C6472 devices more easily and affordably, TI is also offering a multicore processors evaluation module (EVM), the TMDXEVM6472, for USD $349.
With the C6472, TI has broken the power performance barrier by fully optimizing the device for applications where performance per watt is a critical requirement. The C6472 DSP offers the lowest power consumption with the highest processing performance of any multicore DSP with the total of 3GHz performance in the market, performing at 3.7W performance and 0.15 mW/MIPS. TI’s power-efficient C6472 was designed to support applications that drive many channels, demand maximum performance density and for which designers must have access to sophisticated functions. Additionally, many applications utilizing the C6472 will not require any external memory, further improving the power profile and cost effectiveness of the device.These devices are ideal for markets such as high-end industrial, test and measurement, communication, medical imaging, high-end imaging and video, and blade server. TI provides extensive support for the C6472, including an evaluation module, robust software libraries and a third-party ecosystem, to further facilitate the process of writing code that runs optimally on multicore devices.
C6472 DSP key features and benefits:
· Six high-speed C64X+ DSP cores running at 500MHz, 625MHz, 700MHz, and fully backward compatible with other C64X DSP cores.
· Up to 4.2 GHz/33600 MMACs and 4.8 MB on-chip L1/L2 RAM.
· Offers best power efficiency in the industry with 3GHz performance at 0.15 mW/MIPS.
· Optimized DSP architecture maximizes subsystem performance on a chip. One of the advantages of this architecture is that in addition to dedicated L1 and L2 memory to each core, the C6472 features 768KB shared L2 program/data memory and a shared memory controller to facilitate high efficient and flexible inter DSP core communications.
· Contains rich device peripherals which include: GigaBit Ethernet, Serial RapidIO (SRIO), DDR2, telecom serial interface port (TSIP), host port interface (HPI), Utopia, Inter-Integrated Circuit (I2C) Bus (I2C) and general purpose input/output (GPIO).