Freescale, Synopsys, Functional verification

Freescale and Synopsys announce multi-year strategic collaboration agreement to increase verification productivity

News Release from: Synopsys Inc
26/10/2009

Synopsys, Inc. has announced the expansion of its verification collaboration with Freescale. The integration of complex hardware enabled by Moore's law, IP, and embedded software content in modern devices is causing a rapid increase in verification complexity. Freescale and Synopsys have broadened their ongoing collaboration to manage this growing complexity. In addition to verification performance, efficiency, and methodology, the expanded collaboration will focus on managing the ever-increasing cost of verification, which can encompass up to 75 percent of the total cost of product development.

“Functional verification comprises the largest portion of our total cost of product development and has a greater impact on our production schedules than any other single factor,” said Dan Cronin, vice president of hardware R&D, Network Solutions Division at Freescale Semiconductor, Inc. “In addition to enabling us to deploy a state-of-the-art environment, our extended relationship is expected to address various verification metrics, including the efficiency of compute farms and productivity of engineers, allowing us to more efficiently manage the exploding total cost of verification.

“The strategic collaboration announced today builds on the successful verification engagement between Freescale and Synopsys over many years,” said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys, Inc. “As one of the early adopters of SystemVerilog, Freescale played an important role in advancing the standard. Our collaboration is now extending beyond this standard. With verification becoming a larger part of overall product development cost, we are collaborating with Freescale to deliver solutions that help manage the total cost of verification.”