EVE, DAC, ZeBu, SoC
EVE Adds New Applications for Leading SoC Emulation Platform Environment
News Release from:
16 May 2012
EVE today announced a variety of new software to expand the capabilities of its ZeBu system-on-chip emulation platform, including power-aware verification, post-run debugging, two vertical application validation platforms, low-power and Flash memory models, and electronic system level tool interfaces
“Today’s emulation platforms have evolved into complex verification environments to address hardware/software integration and embedded software validation of large designs,” remarks Luc Burgun, EVE’s chief executive officer and president. “ZeBu has evolved as well and is now the industry trendsetter, as well as market leader, meeting EVE’s goal to offer the most comprehensive and commercially available hardware/software co-verification solution.”
A new power-aware verification package for ZeBu enables functional verification of power switching in low-power designs. Power islands can be turned on/off dynamically to ensure that power switching does not adversely affect a design’s functional integrity. The first release shipping now supports the Unified Power Format standard.
The ZeBu Smart debug methodology has been enhanced with a new post-run debug capability that provides a deterministic methodology for tracing complex bugs. In a ZeBu emulation run, the entire state of the SoC emulation environment is captured in “frames,” including the design configuration, design under test register and memory states, and the corresponding input stimulus to the DUT.
Post-run debug is particularly valuable when problems are identified deep in a long test run or when problem scenarios are difficult to re-create. With post-run debug features, once a problem is identified, the designer has a mechanism to quickly debug it. With the collected data, a debug run can be initiated at any point, and the captured stimulus can be applied to re-create a problem scenario, eliminating the need to start from the beginning of a long test sequence.
EVE has also expanded its library of ZeBu vertical application validation platforms, now exceeding 30 transactors, virtual bridges and ICE speed-rate adapters to easily integrate ZeBu-emulated SoC designs with system-level verification and validation environments.
The e-zTest PCIe Gen 3 validation platform with up to 16 lanes of support, including a PCIe frame Viewer for debug, is now available, as is a new e-zTest 10Gbit Ethernet validation platform. The ZeBu memory model catalog includes the latest low-power and Flash memory models.
Finally, EVE is unveiling new transaction-level interfaces to leading electronic system level software. These links enable a high-performance, hybrid virtual development environment where software integrated development environments are used to debug software executing on ESL virtual platforms with the available RTL code being run and debugged at accelerated emulation speeds in ZeBu. For leading-edge designs, which typically include 50% or more RTL reuse, engineers can access the more accurate, hybrid hardware/software co-verification environment early in the project and identify timing-related issues not found in a pure ESL virtual platform.
Pricing is available upon request. EVE will offer demonstrations of the entire ZeBu hardware-assisted verification family in Booth #1926 at the 49th Design Automation Conference June 4- 6 at the Moscone Center in San Francisco.