Design
New FPGA-Based Prototyping Solution Delivers Up To 3x System Performance Improvement
Synopsys today announced the availability of Synopsys' HAPS-70 Series FPGA-based prototyping systems, extending its HAPS product line to address the increasing size and complexity of system-on-chip designs. The HAPS-70 systems provide tightly integrated prototyping software and hardware, including high-speed time-domain multiplexing (HSTDM) technology, which in combination with new HapsTrak 3 I/O connectors delivers up to 3x prototype performance improvement over traditional connector and pin multiplexing technology.
IAR Systems improves 8051 development with new user-friendly features
IAR Systems has announced a new version of its compiler and debugger development tool suite IAR Embedded Workbench for 8051. Version 8.20 adds a new editor and source browser, Subversion integration and enhanced debugger drivers.
Sensing a connection
Denny Steele, Director of Strategic Business Marketing for Lattice Semiconductor investigates, in this ES Design magazine article, how the latest low power FPGAs are bringing an extra level of flexibility to smartphone design.
Chris Grujon of TenAsys explores and discusses multicore machinations
OEM products that incorporate real-time technology are complex to develop and validate to a point where they are deemed stable enough to release into the market. Nobody wants a robot to start behaving erratically on the manufacturing floor because of a software bug that wasn't detected due to insufficient testing and validation of the code. Often, the key to being able to deploy new products rapidly is to use as much of an existing, proven code base as possible.
Bringing economies of scale to MEMS
Baolab's release of an evaluation kit for its first MEMS product built in the metal interconnect layer heralds the start of truly low cost and high volume MEMS technology, built within the standard CMOS BEOL process. Sally Ward-Foxton, Contributing Editor of ES Design Magazine reports.
Designing in the Cloud
As more technology moves to the cloud, online application engineering environments are paving the way towards the rapid and collaborative development of complex semiconductor products. By Dr. Uwe Knorr, VP of Marketing & Sales with Transim Technology.
An integral part of PCB
Signal integrity simulation before, during and after PCB design is now one of the most underestimated tasks in electronics product development. Jörg Kaleita, Technical Account Manger from Altium Europe explores and discusses signal integrity simulation in this article from ES Design Magazine.
Synopsys Introduces Memory Test and Repair Solution for Designs at 20 Nanometers and Below
Synopsys today announced a new release of its DesignWare STAR Memory System, an automated pre- and post-silicon memory test, debug, diagnostic and repair solution that enables designers to improve quality of results, reduce design time, lower test costs and optimize manufacturing yield.
High-quality Cloud-based Storage Available Via Apacer’s USB Disk Module
QNAP's cloud-based network storage product, the TS-x79 series, features consistent high-security, high-reliability, handy-to-use and high-efficiency tradition, along with guaranteed VMware ready, Citrix ready and Microsoft Hyper-V compatible certification. The TS-x79 series has become the best storage option for high-end SMBs to go for virtualization cloud. This series ensures stability, security and performance due to the adoption of Apacer's USB disk module as startup disk.
Electrical Redriver Modeling Solution from Agilent
Agilent have today introduced a redriver modeling solution designed to quickly and accurately solve the challenge posed by signal distortion in multigigabit-per-second systems. The redriver modeling solution, available in the Advanced Design System 2012 Transient Convolution Element and SystemVue 2012 AMI Modeling Kit, is used to design electrical redrivers into high-speed chip-to-chip digital links.
Cadence Encounter Technologies Enable Open-Silicon to Reach 2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor
Cadence have announced that Open-Silicon has leveraged the latest innovations from the Cadence Encounter RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nanometer hardening of an ARM dual-core Cortex -A9 processor.
ST adopts Synopsys' volume diagnostics solution for faster yield ramp
Synopsys today announced that ST has adopted Synopsys' volume diagnostics solution company-wide for faster yield ramp. IC product teams must rapidly isolate and correct systematic failure mechanisms to ramp up new IC designs from low initial yield to mature yield in volume production.
RFEL makes FPGA performance available to ARM Software developers
RFEL has announced that it has extended its design service and consultancy range to include Xilinx's new Zynq-7000 All Programmable SoC. This merges together a mature and powerful ARM multicore processing system with the latest, high speed, Xilinx 28nm FPGA programmable logic into a single chip.
Infineon's Trusted Platform Module supports and secures Windows 8
Infineon Technologies today announced that its Trusted Platform Module solution supports and secures the recently introduced Microsoft Windows 8 operating system. Infineon provides a complete solution based on Common Criteria certified TPM hardware and the corresponding software suite aiming at use in communication and office applications.
Atrenta and TSMC Announce SpyGlass IP Kit 2.0 Availability
Atrenta, with TSMC, have announced today the planned availability of IP Kit 2.0. Based on the SpyGlass RTL design platform, IP Kit is a fundamental element of TSMC's soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft, or synthesizable IP.
Inverse Multiplexing over ATM (IMA) Emulator
Our Inverse Multiplexing over ATM (IMA) Emulator application can simulate inverse multiplexing of ATM cell streams over multiple physical links and retrieve the original stream at the far-end from these physical links. The multiplexing of ATM cell streams is performed on a cell-by-cell basis across the multiple physical links. Traffic source can be sequence number, HDL files (containing packets/frames), flat binary file, user-defined frames (ASCII HEX file), and Ethernet data.
Timesys Introduces LinuxLink for Avnet ZedBoard
Timesys Corporation today announced the availability of its award-winning LinuxLink embedded Linux framework for platform and application development to include the Avnet ZedBoard. This latest LinuxLink offering expands Timesys' support for Xilinx SoCs, including the Zynq-7000 All Programmable SoC.
XPM IP designed into MEMS IC accelerometer sensor targeting portable devices and tablets
Kilopass Technology have today announced that its eXtra Permanent Memory IP is designed into a new integrated circuit for a micro electro mechanical systems accelerometer sensor targeting portable devices and tablets. MaruLSI is designing the readout chip for MEMS sensors. XPM's ability to quickly trim at final test analog components that transform a MEMS sensor's analog signals into digital data made it attractive in this application. The ability of XPM NVM IP to be field programmed to offset analog component drift over time due to aging also made it well suited to the MEMS sensor application.
LG Electronics Selects Uniquify’s DDR Memory Subsystems IP for Latest SoC Design
Uniquify announced today that LG Electronics selected its double data rate memory controller subsystem IP for the design of a new consumer entertainment system. LG chose Uniquify's DDR IP with patented, adaptive technology known as Self-Calibrating Logic and Dynamic Self-Calibrating Logic to ensure product system reliability.
STEC's ZeusIOPS SAS SSDs feature in Storagedata SAN 3800 and SAN 5000 systems
Storagedata and STEC have today announced that STEC's ZeusIOPS SAS SSDs are featured in the new SAN 3800 and SAN 5000 systems from Storagedata. The ZeusIOPS SAS SSDs, combined with Storagedata's powerful Storage Management operating system, enable the SAN 3800 and SAN 5000 to deliver outstanding performance -- over 500,000 IOs per second (IOPS) -- and the reliability required by cost-efficient SAN applications.
Record EEMBC CoreMark Benchmark Results for Kinetis Microcontrollers
Green Hills Software has announced that its optimising compilers for ARM Architecture were used by Freescale for published EEMBC CoreMark scores on the Freescale Kinetis K70 90nm microprocessor based on the ARM Cortex-M4. The Kinetis K70's CoreMark/MHz score of 3.08, running at 150 MHz out of flash, represents the highest CoreMark scores ever published for a Freescale Kinetis microcontroller and exceeds all other published results for competing compilers on the same device.
AMD Changes Compute Landscape as the First to Bridge Both x86 and ARM Processors for the Data Center
AMD announced that it will design 64-bit ARM technology-based processors in addition to its x86 processors for multiple markets, starting with cloud and data center servers. AMD's first ARM technology-based processor will be a highly-integrated, 64-bit multicore System-on-a-Chip (SoC) optimized for the dense, energy-efficient servers that now dominate the largest data centers and power the modern computing experience.
Control and connectivity considerations in the design of smart meters by Jonathan Page, MSC Gleichmann
Utility companies and governments are committed to the inexorable deployment of smart meters for a whole variety of reasons. Governments typically see this as part of their "green" strategy in raising awareness of the need to conserve energy and other resources. Utility companies may see this as part of their corporate social responsibility but more likely they will have a much stronger commercial objective.
Microchip’s Free MPLAB XC32++ Compiler for All 32-bit PIC32 MCUs Offers Unlimited Code Generation
Microchip Technology today announced its free C++ compiler with unlimited code generation—the Free MPLAB XC32++ Compiler. The MPLAB XC32++ supports all of Microchip's 32-bit PIC32 MCUs. This compiler enables designers to develop and re-use C++ projects by making all of Microchip's C language extensions available in an environment that is compliant with the majority of C++98 and C++2003 ANSI standards.
TI and AllGo collaborate to offer eTAB Reference Design
Texas Instruments and AllGo Embedded Systems have introduced the new all-in-one Electronic Tablet (eTAB) Reference Design, allowing developers to get to market with a complete, customized enterprise tablet in as little as three months.
Cadence reveal 14nm Test-chip featuring ARM Cortex-M0 processor and IBM FinFET Process Technology
Cadence Design Systems announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.
Latest IAR Embedded Workbench for ARM offers new functionality and compiler optimizations
IAR Systems have launched a new version of its world-leading development tool suite, IAR Embedded Workbench for ARM version 6.50. The new version adds expanded integration and new functionality. In addition, enhancements to the optimization technology in the powerful IAR C/C++ Compiler result in even faster code execution.
Altera first to benchmark DSP designs on 28nm FPGA devices
Altera has today announced the successfull benchmarkmarking of complex, high-performance floating-point DSP designs on 28 nm FPGA devices. Independent technology analysis firm Berkeley Design Technology, Inc. (BDTI) verified the efficiency and ease-of-use of Altera's floating-point DSP design flow as well as the performance of demanding floating-point DSP applications on Altera's Stratix V and Arria V 28 nm FPGA development kits.
Xilinx announce fourth generation secure architecture for defense-grade FPGAs
Xilinx today announced its fourth generation secure architecture with Information Assurance and Anti-Tamper IP core support for defense-grade 7 series FPGAs and Zynq-7000 All Programmable SoCs. These unique high reliability, defense-grade devices reduce the risk and cost of deploying the latest Aerospace and Defense (A&D) systems by utilizing off-the-shelf reprogrammable Xilinx FPGAs and SoCs.
Synopsys Extends Support for ARM AMBA Protocol Verification with New Performance Checker for AMBA 4 AXI4
Synopsys today announced that its next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol now offers a Performance Checker capability. This capability enables system-on-chip (SoC) verification teams to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks.
Forte's Latest Version of Cynthesizer SystemC high-level synthesis (HLS).
Forte Design Systems has revealed today immediate availability of the latest version of its Cynthesizer System high-level synthesis. Enhancements, including increases to Cynthesizer's performance and capacity, have been made across the entire tool suite to enable designs to be done faster and with better results. The latest features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare intellectual property cores.
CST STUDIO SUITE 2013 on show at EuMW 2012
Computer Simulation Technology has today announced that it will be previewing CST STUDIO SUITE 2013 and its new design environment at EuMW 2012, booth #217. The increasingly complex tasks design engineers face today require a large number of sometimes specialised features. Simulation software vendors such as CST have enhanced their tools to accommodate these requirements.
Poly-Platform 2.0 now available for TIs' TMS320C6678 Multicore DSP
PolyCore Software today announced that Version 2.0 of its Poly-Platform multicore software platform, is available for TI's TMS320C6678 digital signal processor, based on the KeyStone multicore architecture.
IBM Rational Rhapsody and LDRA tool suite streamline model to verification process
LDRA has fully integrated the LDRA tool suite with IBM Rational Rhapsody ensuring a seamless workflow from model-driven development to test and verification. IBM Rational Rhapsody, a UML-based modeling and code-generation tool, speeds the design of complex systems that often must meet industry certification standards
Cadence Verification IP Significantly Reduces Verification Turnaround Time for ARM AMBA 4 Protocols
Cadence Design Systems today announced multiple successful verification projects using Cadence Verification IP for ARM AMBA protocols, one of the industry's most widely used verification solutions for the AMBA protocol family.
NXP’s SmartMX2 chosen by The Industrial & Commercial Bank of China
NXP have today revealed that the world's largest bank, the Industrial & Commercial Bank of China, has selected its SmartMX2 high security microcontroller to increase the security and performance of its banking cards. The new cards will have dual interface capabilities that will enable both contact and contactless payments.
AMD Powers Superior Windows 8 Experience Across More Than 125 PC Designs
AMD today announced its collaboration with Microsoft Corp. for more than 125 Windows 8-based PC designs from leading OEMs including ASUS, Dell, Fujitsu, HP, Lenovo, Samsung, Sony, Toshiba and more. With a hardware accelerated user interface, Microsoft and AMD have collaborated to design Windows 8 to unlock the high performance graphics capabilities found in AMD accelerated processing units (APUs) and discrete AMD Radeon graphics processing units (GPUs) to deliver the best HD video, gaming and app experience consumers want with the always on, always connected, touch-driven interface with great battery life they need.
Graphical Audio Development Tool for SHARC Processors from ADI
Analog Devices has today announced the introduction of the SigmaStudio for SHARC graphical development tool for audio applications. Based on ADI's award-winning SigmaStudio for SigmaDSP digital signal processor tool, the SigmaStudio for SHARC tool is a programming, development and real-time tuning software environment that enables developers to graphically design and program audio applications for SHARC processors using an extensive, optimised library of more than 100 pre-built audio algorithms.
Renesas Releases New Version of e2studio IDE for RX and RL78 MCUs
Renesas have today unveiled the release of version 1.1 of its Eclipse-based integrated development environment, e2studio, designed to provide a flexible development platform for its market-leading RX and RL78 microcontrollers.
Renesas Electronics Unveils Next-Generation Microcontroller and Microprocessor Roadmap
Renesas Electronics today disclosed details of its roadmap for next-generation microcontrollers and microprocessors. Among the new developments, Renesas announced plans to use the company's 40 nanometer MONOS embedded flash technology with its RX family of high-performance, general-purpose 32-bit MCUs.
