Design
Timing Diagram Editors offer Editable Analog Equations
SynaptiCAD has released version 15 of its family of Timing Diagram Editors and test bench generators. The major enhancement in the new version is the ability to create blocks of editable analog waveforms using simple Python-based equations.
Express Logic ThreadX Available for Tensilica’s New Third-Generation Diamond Standard Dataplane Processor Cores
Tensilica, Inc. and Express Logic, Inc. today announced that Express Logic's ThreadX real-time operating system (RTOS) is now available for Tensilica's new third-generation Diamond Standard dataplane processor (DPU) cores. A free demo download of the ThreadX RTOS is available on the Tensilica web site at http://www.tensilica.com/partners/operating-systems/express-logic/threadx.htm. Designed for small-footprint, demanding real-time control, the ThreadX RTOS is a perfect match for the Diamond Standard family of general-purpose, low-power cores aimed at deeply embedded control and signal processing functions.
Tensilica Introduces Third Generation ConnX 545CK 8-MAC VLIW DSP Core
Tensilica, Inc. today introduced its third generation ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. Improvements in this third generation dataplane processor (DPU) core deliver up to 20 percent faster clock speed, 11 percent smaller die and up to 30 percent lower power consumption.
Timesys announces support for newest DaVinci TMS320DM368 video processor
Timesys announced that Timesys LinuxLink will now support the recently announced Texas Instruments Incorporated (TI) TMS320DM368 DaVinci™ video processor. Customers will now be able to develop custom Linux products using the DM368 faster by focusing on value-add features and taking advantage of the hardware acceleration.
Lauterbach to provide best-in-class debugging tools and support for Timesys embedded Linux
Timesys and Lauterbach, leader in hardware-assisted microprocessor debugging and development tools, today announced a strategic partnership that enables software developers and system architects to easily and quickly develop embedded Linux products.
eASIC eTools 8.1 Design Suite Reduces Design Time by 40%
eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.1 Design Suite for implementing 45nm Nextreme-2 designs. The eTools 8.1 tool suite delivers a robust ASIC grade design flow with the simplicity and ease of design that is normally associated with FPGA design tools. New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40% while increasing design performance by up to 30% compared to the previous eTools 8.0 suite.
eASIC Nextreme Used for Hardware Validation of Microsoft RemoteFX Technology
eASIC Corporation today announced that it is working with Microsoft Corp. on using eASIC's Nextreme NEW ASICs to create a hardware implementation of the Microsoft RemoteFXTM technology, which was announced two months ago. eASIC's Nextreme product has been able to quickly validate the Microsoft RemoteFX technology in silicon and to attract a growing ecosystem of companies interested in developing eASIC-based solutions that accelerate the adoption of remote and shared resource computing applications.
NXP Announces Availability of CGV High Speed Converter Demonstration Boards based on LatticeECP3 FPGAs
NXP Semiconductors today announced the availability of two low cost, low power demonstration boards for its CGV™ high speed data converter family, based on the Lattice Semiconductor (NASDAQ:LSCC - Hillsboro, Oregon) LatticeECP3™ FPGA. The demo boards are designed to demonstrate the interoperability of NXP's CGV converters with Lattice's ECP3 FPGA family. One demo board features the NXP ADC1413D and the Lattice ECP3 device, while the other board features the NXP DAC1408D and the LatticeECP3 device. NXP will demonstrate the ADC1413D demo board at the IEEE Microwave Theory and Techniques Society (MTT-S) / International Microwave Symposium (IMS) Conference in Anaheim, California from May 25-27. NXP's booth number is 3324.
Imagination Technologies licenses high-performance multi-processor graphics processor core to Texas Instruments
Imagination Technologies Group plc (LSE: IMG; Imagination), a leading multimedia and communications chip technologies company, has signed a multi-use license agreement with Texas Instruments Incorporated (TI) for a multi-processor solution from Imagination's new POWERVR SGX Series5XT Graphics Processing Unit (GPU) IP core family.
Computer Simulation Technology (CST) announces closer cooperation and webcast with Cadence Design Systems, Inc.
To address increasing customer demand for integrated layout and 3D full wave analysis, CST and Cadence are collaborating to provide a best in class solution. A webcast on June 23 will demonstrate the integration.
Aegis Software Selected by Makso Electronic BV
Aegis Software announces that its New Product Introduction and shop-floor paperless documentation system has been selected by Makso Electronic BV for their manufacturing site in Veenendaal, The Netherlands. Their deployment integrates all of operations from New Product Introduction through documentation version control and viewing on the production floor. Through use of Aegis' singular system architecture, their process planning, documentation and programming functions are unified with shop-floor document delivery and control. This delivers Makso both world-class NPI velocity and work instruction management. Their engineering offices turn jobs and ECO's rapidly while operators have version-assured access to CAD-intelligent and visual work instructions across the entire process scope.
EdXact to Enhance Interactive Debugging Capabilities, Hierarchical File Handling and Improved Selectivity Features to Its Post-Layout Analysis Tools at 47th DAC
EdXact, post-layout verification specialist will showcase the latest tool enhancements of its parasitics reduction and analysis tools. Among the highlights of the tool releases 5.0 of Jivaro™ and 3.2 of Comanche ™are hierarchical file handling, additional features to drive the selectivity options and integrations into different graphical user interfaces in order to facilitate interactive network debugging facilities.
Forte Unveils Cynthesizer Ultra, Next-Generation High-level Synthesis
Forte Design Systems today launched Cynthesizer Ultra, its high-level SystemC synthesis software tightly integrated with its CellMath product family to create better designs faster. Additionally, Forte's flagship Cynthesizer SystemC high-level synthesis software, used in more than 200 production ASIC and SoC silicon tapeouts since 2002, includes new capabilities that reduce design time, improve power utilization and accelerate verification performance.
Synopsys’ IC Compiler widely deployed at MediaTek
Synopsys announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, has standardised on Synopsys' IC Compiler physical design solution, a key component of the Galaxy Implementation Platform, to deliver best performance, power and area on MediaTek's leading-edge wireless communications chips. IC Compiler's advanced placement, timing and power optimisation along with its tight correlation to signoff has contributed to faster design closure.
Magma's Titan ALX and Titan AVP gives Layout Productivity Improvement for Analog/Mixed-Signal Designs
Magma Design Automation a provider of chip design software, today announced Titan™ Analog Layout Accelerator (ALX) and Titan Analog Virtual Prototyper (AVP), new tools that accelerate the creation and optimization of new analog design layouts, and automate the reuse of existing analog layouts in new processes and technologies.
Real Intent Improves Its Fast, Low-Noise Electronic Design Linter; Ascent Lint Version 1.3 Extends High-Performance Linting to VHDL
Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, announced today that it is shipping a new version of Ascent Lint Version 1.3. The new version adds VHDL checks to its existing Verilog checks.
Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology
Xilinx introduced the ISE Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity. For the first time, ISE design tools deliver 'intelligent' clock-gating technology that reduces dynamic power consumption by as much as 30 percent. The new suite also provides advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications.
Xilinx Unveils ARM-Based Processing Architecture for Delivering Unrivaled Levels of Performance in Embedded Systems
Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform that will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
Xilinx and Hitachi Information & Communication Engineering Announce New Virtex-6 FPGA-Based LogicBench Series Platform for System-Level Design Verification in Japan
Xilinx K.K., the Japanese subsidiary of the world's leading supplier of programmable platforms, Xilinx, Inc., andHitachi Information & Communication Engineering, Ltd., today announced a new LogicBench series. LogicBench is proven system-level design verification platform. The new series uses Xilinx Virtex-6 LX760, the fastest and highest performance FPGA, and other Virtex-6 FPGA sub-families. Hitachi Information & Communication Engineering also launched sales for the Japanese domestic market today.
LSI Announces Development System for Enterprise Video Applications
LSI Corporation announced the availability of a media processing development system based on the LSITM SP2704 StarPro media processor, which extends the LSI asymmetrical multicore architecture to enterprise video applications using the company's proven family of networking silicon and software. The new development system allows OEMs to build media-aware networks that enable intelligent media and graphics processing in the data center and enterprise network.
Cadence Accelerates SoC Realization, Reduces Costs With New Open Integration Platform
Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, today announced the Cadence Open Integration Platform, a platform that significantly reduces SoC development costs, improves quality and accelerates production schedules.
VIA’s Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65 Nanometers
Cadence Design Systems, the global leader in EDA360, today announced that VIA Technology's microprocessor subsidiary, Centaur Technology, achieved significant quality and time-to-market benefits by using the Cadence® Virtuoso® Space-Based Router on its latest set of processors. Centaur used the Cadence router to help design its new 65-nanometer Nano 3000 Series processors, designed to bring enhanced digital media performance and lower power consumption to Windows 7 notebook and desktop PC markets. Centaur adopted the Space-Based Router for 65-nanometer custom datapath designs and standard cell routing.
Cadence Issues Blueprint to Battle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat
Cadence Design Systems today laid out a new vision for the semiconductor industry, EDA360. In outlining an application-driven approach to system design and development, Cadence issued a challenge to the semiconductor and electronic design automation (EDA) communities to address the growing "profitability gap" that threatens the vitality of the electronics industry.
Cadence Debuts Verification Computing Platform, Accelerating Time and Improving Quality of System Development
Cadence Design Systems announced the first fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better quality embedded systems in a shorter time.
Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips
Cadence Design Systems announced that it has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.
Synaptics Gesture Suite Now Available For Popular Linux Operating Systems
Synaptics Inc. (NASDAQ: SYNA), a leading developer of human interface solutions for mobile computing, communications, and entertainment devices, today announced the extension of its industry-leading Synaptics Gesture Suite™ to the Linux operating system environment. This release extends the Synaptics Gesture Suite—which includes sophisticated multi-finger gestures—to OEMs that offer Linux-based solutions.
TI's new FilterPro v3.0 design tool eases amplifier filter design
Texas Instruments introduced the latest version of its popular FilterPro design tool. FilterPro v3.0 offers a new and improved user interface and a more accurate and robust filter design engine, thanks to updates, such as ability to adjust passive element tolerances and view response variations; scale passive component values; and view and export filter performance data to Excel.
Green Hills Software INTEGRITY RTOS available on all Extreme Engineering Solutions, Inc. (X-ES) boards with Intel® Core™ i7 processors
Green Hills Software and Extreme Engineering Solutions, Inc announced the availability of INTEGRITY RTOS board support packages (BSPs) on all Extreme Engineering Solutions embedded computing products based on the new Intel Core i7 processor.
Teridian Semiconductor Corporation Approves Datatronics Modem Transformer For Reference Designs
Teridian Semiconductor Corporation has approved the new Model PT79281 V.22bis Modem Transformer from Datatronic Distribution, Inc., for use with its reference designs that include the Teridian IC Models 73M1903, 73M1903C, 73M2901CE and 73M2901CL.
Magma Announces SiliconSmart ACE Memory Characterization – Embedded FineSim Pro Enables Most Accurate Characterization of Timing, Power and Noise Models
Magma Design Automation announced SiliconSmart ACE Memory Characterization, the latest addition to the industry-standard SiliconSmart IP characterization and modeling product line. By embedding Magma's ultra-fast FineSim Pro simulator and leveraging Magma's proprietary optimization technology for memory circuits, SiliconSmart ACE Memory Characterization provides faster, more accurate timing, power and noise characterization of memory instances than competitive tools. With SiliconSmart ACE Memory Characterization, integrated circuit (IC) designers can reduce turnaround time and deliver better results for designs targeted at 28-nanometer (nm) and smaller process nodes.
Magma’s Titan Supports IPL 1.0 Standard for Interoperable Process Design Kits
Magma Design Automation announced today that the Titan Mixed-Signal Platform has been validated to support the interoperability and accuracy requirements of the IPL 1.0 Interoperable Process Design Kit (iPDK) standard. The Interoperable PDK Libraries (IPL) Alliance standard eliminates the need to develop multiple proprietary PDKs and design databases, reducing development costs, shortening delivery schedules and providing designers earlier access to new advanced process technologies across multiple tools. The combination of Titan's advanced capabilities and compliance with the IPL 1.0 standard provides designers with the fastest path to mixed-signal silicon.
Altium - Learn to eliminate risk and get designs right, first time
Learn how to eliminate the fear and uncertainty of releasing an electronics design to production at Altium's webinars 'Right First Time: Design Configuration and Release Process Management'. The first English webinar will take place on May 19, 2010 at 2 pm CEST,12 pm GMT (at 10 am CEST in German, at 1pm CEST in French).
VarioTAP supports non JTAG Interfaces
During its „Boundary Scan Days Germany", GOEPEL electronic introduced the further development of the innovative emulation technology VarioTAP for the support of non JTAG debug interfaces. The new features enable the broad coverage of various proprietary debug architectures of different chip manufacturers without utilising processor specific pods. The first interfaces to be supported are the so called BDM interface (Background Debug Mode) and the MCU of the Freescale MPC5xx series with power architecture. The available functionality of VarioTAP® ranges from Flash programming up to emulation test at system level.
Wittenstein: SafeRTOS SIL3 Compliant RTOS available for Texas Instruments SIL3 Compliant MCU
WITTENSTEIN High Integrity Systems has announced SafeRTOS is available for the SIL3 compliant Texas Instruments TMS570LS microcontroller family for safety related applications.
Altium Designer helps students at Leipzig University prepare for the future
Students at the Institute of Process Automation and Embedded Systems at Leipzig University of Applied Sciences for Technology, Economics and Culture, are now taking the unified approach to their electronics design projects.
Magma Announces SiliconSmart ACE Memory Characterization – Embedded FineSim Pro Enables Most Accurate Characterization of Timing, Power and Noise Models
Magma Design Automation just announced SiliconSmart ACE Memory Characterization, the latest addition to the industry-standard SiliconSmart IP characterization and modeling product line. By embedding Magma's ultra-fast FineSim™ Pro simulator and leveraging Magma's proprietary optimization technology for memory circuits, SiliconSmart ACE Memory Characterization provides faster, more accurate timing, power and noise characterization of memory instances than competitive tools. With SiliconSmart ACE Memory Characterization, integrated circuit (IC) designers can reduce turnaround time and deliver better results for designs targeted at 28-nanometer (nm) and smaller process nodes.
Advanced technology for design, modelling and high-performance simulation saves engineers time and effort
MapleSim 4 introduces a new 3-D construction feature, which saves engineers significant time when developing multibody models. MapleSim provides instant, realistic feedback of multibody systems by dynamically rendering the model as it is built. In addition, the 3-D construction environment lets engineers add and manipulate multibody components directly in the 3-D workspace. Other new features include flexible probe management tools, including an easy way to add new probes to previous simulation results without having to rerun the simulation; a new semi-stiff solver that provides good results for stiff systems without the overhead formulation costs of a true stiff solver, and new and enhanced analysis tools, including tools for working with multibody equations.
Latest Synopsys IC Compiler release delivers more than 2X speed-up, enhanced In-Design technology and production support for 28/32nm
Synopsys announced the availability of IC Compiler 2010.03, a physical implementation solution delivering up to 2.5X faster performance on multicorner/multimode (MCMM) designs, and enhanced In-Design technology for faster design closure. IC Compiler's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has production support for all known 28/32nm design rules for major foundries, with several customer tapeouts underway.
Synopsys Unveils Ethernet Controller IP With New Audio Video Bridging Feature
Synopsys announced the immediate availability of the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications.
Synopsys launches MIPI DigRF v4 IP & speeds LTE and WiMAX SoC development
Synopsys announced the immediate availability of the DesignWare MIPI 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards.
