Xtensa, DPU, Tensilica

Tensilica Announces Enhanced Tools for Dataplane Processor Design and Software Development

News Release from: Tensilica
07 December 2009

Tensilica has announced its eighth generation tools that further automate customized Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL.

These enhancements further strengthen Tensilica's leading position as the highest performance, and most complete, customizable processor core solution for SOC (system-on-chip) designs.

In the dataplane - as opposed to the control plane - our DPUs have to deal with intensive data processing workloads and direct interconnection to hardware blocks, stated Steve Roddy, Tensilica's vice president of marketing and business development. With this eighth generation tool set, we've concentrated on improvements that make it easier for designers to use customized DPUs to perform these data-intensive tasks, bringing programmability, enhanced debugging, and post-silicon software upgradability to signal processing and other dataplane functions previously handled in dedicated hardware blocks.