NI LabVIEW FPGA IP Builder software incorporates HLS Improve FPGA Design Productivity
News Release from:
03 August 2012
National Instruments has today introduced the LabVIEW FPGA IP Builder add-on, which uses leading Xilinx Vivado High-Level Synthesis technology to simplify high-performance field-programmable gate array algorithm design. This new LabVIEW add-on enhances productivity by reducing the need for manual optimisation of high-performance algorithms.
Instead, users specify functional behaviour along with design constraints and the software automatically generates a hardware implementation to meet requirements.
The new add-on tightly integrates with LabVIEW and the LabVIEW DSP Design Module, a LabVIEW module that helps researchers and system designers in the RF and telecommunications space quickly create communication links and multirate digital signal processing algorithms on FPGAs.
“Our vision for the LabVIEW platform is to empower domain experts to represent their algorithms using natural programming paradigms and provide a seamless path for deploying to high-performance hardware,” said David Fuller, Vice President of Applications and Embedded Software for NI. “High-level synthesis technology is central to this vision – it empowers system designers to spend less time optimising their FPGA algorithms and more time innovating.”
•Increased FPGA design abstraction for enhanced productivity
•Improved algorithm performance and resource utilisation
•Separation of code and design constraints facilitates IP reuse
•Seamless deployment to NI FPGA-based devices and integration with I/O