EnSilica, eSi-RISC Development Suite v2.1
EnSilica launches major new version of its eSi-RISC Development Suite
News Release from:
29 March 2010
EnSilica, a leading independent provider of front-end IC design services, has launched a major new version of its eSi-RISC Development Suite. The eSi-RISC Development Suite v2.1 provides a comprehensive platform for easily evaluating EnSilica's family of eSi-RISC highly configurable and low-power soft processor cores, along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.
The eSi-RISC Development Suite v2.1 includes a new hardware evaluation platform based on Altera’s Cyclone III FPGA with rapid software development and debugging facilitated through the Eclipse IDE (Integrated Development Environment) and industry-standard GNU GCC 4.4.0 toolchain, which now features native support for the eSi-RISC architectural features. FPGA configurations are supplied for the complete eSi-RISC processor family, along with numerous application examples demonstrating how the system-on-chip peripherals can be used, including a full port of the open source FreeRTOS with lwIP TCP/IP network stack. Comprehensive documentation and a range of interactive tutorials are also included.
Extensive debug facilities in the eSi-RISC Development Suite v2.1 also significantly enhance development productivity. Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly. Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.
The eSi-RISC Development Suite v2.1 also allows developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics’ ModelSim from the Eclipse GDB project debugger through a network socket connection. ModelSim conveniently displays disassembled instructions as text in the wave display which is especially helpful for SoC level hardware and software debugging.
Network application debugging is also considerably simplified with the integration of WinPcap into the new eSi-RISC Development Suite’s Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. This makes it possible, for instance, to run a Web Server on eSi-RISC with a live Ethernet connection serving web pages to a browser running on a remote computer.
“The ease and speed with which processors can be evaluated and applications developed and tested, plays an important role in developers’ choice of processors,” said Ian Lankshear, Managing Director of EnSilica. “The eSi-RISC Development Suite v2.1 includes a host of new features and capabilities to enable our eSi-RISC processor family to be easily evaluated and quickly deployed.”