Cadence, Physical Verification, TSMC qualify
Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process
News Release from:
Cadence Design Systems
06 June 2012
Cadence Design Systems, Inc. today announced that TSMC has qualified the Cadence Physical Verification System for 28-nanometer design signoff, and completed Phase I certification for TSMC's 20-nanometer process. Designers can request a PVS 20-nanometer technology file directly from TSMC for early design exploration, and access TSMC-Online to download 28-nanometer technology files for signoff.
Cadence PVS supports 20-nanometer technology where innovative patterning technology is used. The dedicated PVS engine improves color loop detection accuracy, reduces false errors and provides intuitive error reporting. The Cadence technology also ensures mask decomposition feasibility.
Cadence PVS is integrated with Cadence Virtuoso custom and Encounter digital implementation platforms to help designers find and fix errors early in the implementation stage. Integration with Virtuoso includes real-time, in-design design rule checking verification; real-time 20-nanometer DPT color loop detection; and incremental DRC correction and verification.
“Our work with TSMC helps ensure that design teams will have advanced implementation and signoff technologies available for SoC design and manufacturing,” said Chi-Ping Hsu, senior vice president of research & development, Silicon Realization Group. “TSMC’s qualification of Cadence PVS at 28 nanometers and early certification for 20 nanometers represents an important joint commitment to deliver convergent verification capabilities for today’s complex mixed-signal SoCs.”
“PVS has successfully completed TSMC’s qualification process for 28-nanometer design signoff,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We worked closely with Cadence to achieve these results, including technical collaboration on 20-nanometer advanced technology.”