PAC-Designer mixed signal design software
Lattice announces new version of mixed signal design software
News Release from:
Lattice Semiconductor Corporation
12 December 2011
Lattice Semiconductor Corporation today announced release 6.2 of its PAC-Designer mixed signal design software, with updated support for Lattice's Platform Manager, Power Manager II and ispClock devices. Users designing with Platform Manager devices now have more integrated access to the Lattice Diamond 1.4 software design environment, also announced today.
The advanced integration of the PAC-Designer 6.2 and Diamond 1.4 design software tools make more advanced digital design options available for Platform Manager products. Features such as reduced LogiBuilder code size, simplified design flow and better access to external Platform Manager pin-to-pin connections are among the improvements included in PAC-Designer release 6.2.
“Improvements in the latest PAC-Designer 6.2 and Lattice Diamond 1.4 software tools raise our customers’ ability to design and simulate Platform Manager devices to new levels,” said Shyam Chandra, Lattice Product Marketing Manager for Mixed Signal Products. “The ability to simulate external pins enables platform-level logic simulation that significantly increases the likelihood of first time success, resulting in reduced time to market.”
Comprehensive Analog and Digital Design Flow
PAC-Designer 6.2 software provides an easy to use GUI-based design methodology for configuring the Platform Manager’s analog sections. To implement more advanced digital board management functions, Lattice Diamond Verilog/VHDL design tools are available for use with the same design. Once a design is implemented, a complete simulation environment is created that includes automatic stimulus template file generation.
PAC-Designer 6.2 software includes reference designs specifically targeted for the Platform Manager development kit.
Third Party Design Tool Support
The integrated PAC-Designer 6.2 and Lattice Diamond 1.4 software both include the Synopsys Synplify Pro advanced FPGA synthesis for Windows. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows.
In addition to the tool support provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
About the Platform Manager Family
The innovative Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power management section and a digital board management section. The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.
Pricing and Availability
PAC-Designer 6.2 and Lattice Diamond 1.4 software are available immediately for free download from the Lattice website at www.latticesemi.com/products/designsoftware/pacdesigner/index.cfm