Lattice ships first samples of LatticeECP4 FPGAS
News Release from:
Lattice Semiconductor Corporation
08 June 2012
Lattice Semiconductor Corporation today announced that it has begun shipping the highest density member of its next generation LatticeECP4 FPGA family to select customers. The new LatticeECP4 FPGA family offers the richest portfolio of low cost, low power mid-range devices under 200K LUTs, with high performance innovations such as 6G SERDES in low cost packages, powerful DSP blocks and built-in hard IP-based communication blocks.
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro basestations, small cell stations, pico stations, microwave and millimeter-wave backhaul links. The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The powerful DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the device’s low power and economy, said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. “The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.”
Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. Lattice Diamond design software is the flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enable designers to more quickly target low power, cost-sensitive FPGA applications. In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include a very accurate power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.